Happy Monday! Here’s what’s inside this week’s newsletter:
Deep dive: Following last week’s overview, we examine how advanced packaging uses 2D, 2.5D, and 3D integration to organize chips within packages, and how interposers enable dense, power-efficient connectivity between them.
Spotlights: Nscale’s $433M follow-on round days after its $1.1B funding, and a new report projecting a 46.8% CAGR for the neuromorphic chip market as brain-inspired computing moves toward commercial adoption.
Headlines: Geopolitical shifts in the global chip race, hybrid memory, a new €300M quantum fund, advances in photonics and neuromorphic computing, and major developments across data centers, cloud, and AI.
Readings: Developments in AI co-processors, quantum entanglement explained, China’s photonics ambitions, wafer-scale neuromorphic fabrication, and new approaches to AI models using sparse attention.
Funding news: Later-stage financings dominated the week, led by Cerebras Systems’ $1.1B round (after which it withdrew it’s IPO plans), alongside active deals in semiconductors, cloud, photonics, and quantum.
Bonus: Europe’s Chips Act 2.0 initiative gathers momentum as all 27 EU member states call for semiconductors to be treated as a strategic industry on par with aerospace and defence.
Deep Dive: Advanced Packaging Pt. 2 – How Integration and Interposers Reshape Chips
Last week we covered the fundamentals of advanced packaging: why it matters, what drives adoption, which package types have become essential, and recent developments such as heterogeneous integration, new bonding methods, and thermal management solutions.
This week, we focus on two other critical topics: advanced package-level integration (2D, 2.5D, and 3D stacking) and interposers. Together, they form the foundation for how chips are organized within packages and linked through dense interconnects.
Package-Level Integration: Arranging Multiple Chips
New integration methods redefine how chips are connected within a package, enabling higher performance and efficiency:
2D Packaging
Purpose: The baseline approach where a die is mounted directly on the substrate, mainly for low-cost and mature applications.
Advantages: Simple, inexpensive, and well established.
Limitations: Bandwidth is restricted and scaling options are limited, making it unsuitable for high-performance designs.
2.5D Packaging
Purpose: Places multiple dies side by side on an interposer (explained below) to enable wider, faster interconnects between them.
Advantages: Provides high bandwidth and is less complex than full 3D stacking. Widely used for integrating processors with HBM memory.
Limitations: Interposers add cost and design complexity and can introduce thermal challenges.
Note: Although HBM (High Bandwidth Memory) is itself a 3D-stacked memory device, at the package level it is typically integrated alongside a processor on an interposer. This makes its overall configuration part of a 2.5D package.
3D Packaging
Purpose: Stacks dies vertically and connects them using through-silicon vias (TSVs) and microbumps for the shortest possible interconnects.
Advantages: Delivers the highest density and performance, with very high bandwidth and low power per bit. Key for memory and cache.
Limitations: Thermal management is difficult because heat accumulates in the stack. Yields can be lower and costs higher.
In practice, real-world designs often combine 2.5D and 3D approaches, for example, compute chiplets and I/O chiplets arranged next to stacked memory. This mix is sometimes referred to as 3.5D.
Interposers: Adding a Layer of Connectivity
As chips demand thousands of connections, routing all signals directly on organic substrates (the base layers that mechanically support the package and provide wiring to the circuit board) becomes impractical.
Interposers, the key enabling component in package-level integration discussed above, add an intermediate connection layer between the dies (the individual silicon chips) and the substrate.”
Interposers bring four main advantages over package substrates and printed circuit boards (PCBs):
Enables higher routing density, allowing a larger number of fine-pitch connections.
Keeps more die-to-die interconnects within the package rather than routing through the PCB.
Provides shorter connection paths, which improve signal integrity and reduce latency.
Reduces the required drive strength, lowering overall power consumption per signal.
The tradeoffs are cost, thermal management, and design complexity. For example, HBM must sit close to processors for speed, but DRAM is heat-sensitive, so placement can create reliability risks.
Source: Advanced Packaging Fundamentals (SemiEngineering, 2025)
Spotlights
“Nscale, the UK-based AI data centre startup, has closed a $433 million funding round, just days after bagging a $1.1 billion funding round, as the vast investment in AI infrastructure shows no signs of abating.
Nscale, which pitches itself as a "hyperscaler engineered for AI", was named as a key local AI infrastructure partner for OpenAI, Microsoft and Nvidia, which announced significant investments into the UK AI ecosystem last week, coinciding with the visit of President Trump.”
The neuromorphic chip market, focused on brain-inspired processors that enable fast, low-power, real-time learning, is projected to grow from USD 97.3 million (2023) to USD 3.06 billion by 2032, at a CAGR of 46.8% (2024–2032). Growth is driven by rising demand for AI, robotics, autonomous systems, and edge computing, where efficiency and real-time decision-making are critical.
Challenges include high R&D costs, limited software standardization, and integration hurdles, while opportunities lie in advancements in medical imaging, brain-computer interfaces, driver assistance, IoT, and smart city infrastructure.
The long-term outlook is highly positive as neuromorphic chips move from experimental to commercial use, becoming a core element of next-generation intelligent systems and enabling advances in autonomous technologies, real-time analytics, and adaptive computing.
Headlines
Last week’s headlines covered semiconductor moves from new AI hardware to hybrid memory and chiplet advances, continued momentum in quantum and photonics, breakthroughs in neuromorphic tech, updates in data centers and cloud, new 6G tools, and AI model launches.
🦾 Semiconductors
Huawei Plans Three-Year Campaign to Overtake Nvidia in AI Chips (Bloomberg – Paywall)
Sources: Naveen Rao’s new AI hardware startup targets $5B valuation with backing from a16z (TechCrunch)
Meta acquires RISC-V chip startup Rivos – report (Data Center Dynamics)
Cerebras Withdraws IPO Plans (CNBC)
⚛️ Quantum
55 North Announces First Close For €300 Million Quantum Technology Fund (The Quantum Insider)
Quantum Oscillations Realize Tunable Transitions Between Excitonic and Quantum Spin Hall Insulators in Moiré WSe2 (Quantum Zeitgeist)
Path to Utility Scale for Diraq’s Quantum Chips (Quantum Zeitgeist)
Scientists Create Carbon Nanotube-based Superconducting Quantum Bit (The Quantum Insider)
Scientists Explore New Spin on Quantum Computing (The Quantum Insider)
ESA Continues to Bet Big on Quantum Comms (Payload Space)
⚡️ Photonic / Optical
Alchip and Ayar Labs Unveil Co-Packaged Optics for AI Datacenter Scale-Up (Ayar Labs)
‘Photonic crystal highway’ guides light forward on chips (Laser Focus World)
🧠 Neuromorphic
UMass Engineers Create First Artificial Neurons That Could Directly Communicate With Living Cells (UMass Amherst)
💥 Data Centers
GlobalFoundries and Corning Collaborate To Deliver Detachable Fiber Connector Solutions to Scale Next-Generation Optical Connectivity (GlobalFoundries)
☁️ Cloud
SAP Sovereign Cloud Mindset Even More Valuable than $22 Billion Investment (Cloud Wars)
How Huawei Plans to Open Its Cloud AI Software Stack for Multi-Vendor Deployment (Cloud Computing News)
📡 Connectivity
🤖 AI
Ex-OpenAI CTO Mira Murati introduces Tinker, an API for fine-tuning of open-weight LLMs (The Decoder)
Readings
This week’s reading list includes developments in AI co-processors and packaging, quantum entanglement explained, China’s photonics ambitions, large-scale neuromorphic fabrication, smarter edge data center design, and new approaches to long-context AI models.
🦾 Semiconductors
The Rise of AI Co-Processors (SemiEngineering) (16 mins)
Smarter Packaging: How AI is Reshaping Assembly and Materials Control (SemiEngineering) (25 mins)
Global Semiconductor Foundry Market Share (Counterpoint Research) (5 mins)
Report: Global Processor Market (Yole Group) (15 mins)
Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI (arXiv) (30 mins)
⚛️ Quantum
The Conversation: ‘Spooky Action at a Distance’ – A Beginner’s Guide to Quantum Entanglement And Why it Matters in the Real World (The Quantum Insider) (10 mins)
11 Quantum Startup Operators to Watch in Europe (Sifted – Paywall) (12 mins)
⚡️ Photonic / Optical
China positions itself to lead in future technologies like photonic chips (MERICS) (5 mins)
Ultrabroadband Plug-and-Play Photonic Tensor Core Packaging with Sub-dB Loss (Science Advances) (37 mins)
🧠 Neuromorphic
Wafer-scale Fabrication of Memristive Passive Crossbar Circuits for Brain-Scale Neuromorphic Computing (Nature Communications) (41 mins)
A Comparative Review of Deep and Spiking Neural Networks for Edge AI Neuromorphic Circuits (Frontiers in Neuroscience) (23 mins)
💥 Data Centers
Telcos Are Sitting on Untapped Gold. Here’s a Roadmap to Unlock It (DataCenterDynamics) (6 mins)
Unlocking the Power of Edge Computing Through Smarter Data Center Design (DataCenterDynamics) (7 mins)
🤖 AI
DeepSeek-V3.2-Exp: Boosting Long-Context Efficiency with DeepSeek Sparse Attention (GitHub) (15 mins)
Funding News
Last week was dominated by later-stage, large-scale financings across the computing stack. Cerebras Systems raised $1.1B (and withdrew it’s IPO plans shortly after — see above), while Nscale secured an additional $433M “Pre-Series C” SAFE just days after its $1.1B Series B. Other sizable rounds spanned semiconductors, cloud, photonics, and quantum, underscoring continued momentum in advanced infrastructure.
Amount | Name | Round | Category |
|---|---|---|---|
$6.8M | Photonics | ||
€13M | Quantum | ||
$50M | Data Centers | ||
$87M | Cloud | ||
$250M | Semiconductors | ||
$300M | Cloud | ||
$433M | Data Centers | ||
$1.1B | Semiconductors |
Bonus: Chips Act 2.0 – Europe’s Semiconductor Push
EU governments have declared an “urgent need” for an ambitious follow-up to the 2023 Chips Act. In a joint declaration presented to the European Commission on September 29, all 27 member states called for semiconductors to be treated as a strategic industry on par with aerospace and defence.
The text sets out priorities to secure Europe’s strategic autonomy, strengthen technology leadership across the value chain, and enable faster commercialisation of innovation. Policy goals include:
Boosting R&D from early stages through first industrial deployment.
Aligning national, EU, and private investment with a secured semiconductor budget line for 2028–34.
Setting measurable targets with regular evaluations.
Scaling up production capacity, greener manufacturing, and workforce skills.
Encouraging international joint ventures with “like-minded” partners.
The push comes after the European Court of Auditors warned earlier this year that the EU is “far off the pace” to double its global market share to 20% by 2030. Backed by 75 companies and research organisations under the Dutch-led Semicon Coalition Europe, the declaration now awaits Commission action.
Semicon Coalition & Industry: A United Front to Power Europe’s Semiconductor Future (ESIA - Official joint declaration)
EU Governments Set Out Priorities for Chips Act 2.0 (Science Business)
