🦾 Advanced Packaging — Where Chips Gain Performance

A Newsletter for Entrepreneurs, Investors, and Computing Geeks

Author

Emily Eisenblätter
September 29, 2025

Happy Monday! Here’s what’s inside this week’s newsletter:

  • Deep dive: Why advanced packaging has become a cornerstone of modern semiconductors, how different package types work, and recent developments such as heterogeneous integration, new bonding methods, interposers, and thermal management solutions.

  • Spotlights: HSBC and IBM’s world-first empirical evidence that current quantum computers can add value in real-world trading, and imec’s breakthrough single-patterning High-NA EUV results proving a path toward sub-2nm logic nodes.

  • Headlines: Semiconductor developments from space-grown materials to new transistor designs, a landmark proof of quantum advantage with advances in qubits and quantum internet, and further updates in photonic, neuromorphic, data centers, cloud, and AI.

  • Readings: AI’s role in EDA (Electronic Design Automation) tools, chiplet interoperability, mapping the global quantum landscape, momentum in photonics, co-design for spiking neural networks, and new cooling approaches for data centers.

  • Funding news: A wide spread of financings, from early-stage rounds in encryption, cooling, and quantum, to larger raises in semiconductors and connectivity, led by Nscale’s $1.1B Series B.

  • Bonus: In light of Nvidia’s $100B bet on OpenAI, we explore how the data center race is being reshaped, with Oracle, SoftBank, and Alibaba expanding their roles in building the next generation of AI infrastructure.

Deep Dive: Advanced Packaging — Where Chips Gain Performance

Defining Advanced Packaging

Semiconductor packaging refers to the housing that surrounds a silicon die (a small piece of silicon containing the chip’s circuits), providing both physical protection and the electrical connections needed to link it to a circuit board.

Packaging began as a way to protect fragile chips, but over time it has become one of the most critical enablers of performance. Advanced packaging integrates multiple components into a single unit, often arranged side by side in 2.5D configurations or stacked vertically in 3D structures.

Drivers of Advanced Packaging

There are two main reasons why advanced packaging has become essential: higher bandwidth and lower power.

Higher bandwidth is needed because traditional packages limit the number of signals that can leave the die due to pin spacing (the distance between the electrical connection points on a chip). By routing signals inside the package instead of across a printed circuit board (PCB), advanced packaging enables much denser interconnects and therefore achieves higher bandwidth.

Lower power is equally important. The energy required to transmit a signal increases with distance. PCB traces often span centimeters, while intra-package traces are only millimeters long. These shorter distances reduce the drive strength needed, which lowers the energy per signal. Even if total energy consumption rises because more signals are transmitted, advanced packaging still delivers lower power per bit.

Key Types of Advanced Packaging

Advanced packages differ in how they connect chips to the board and to each other.

  • Lead arrays distribute connections across the entire chip, supporting thousands of short, efficient links. This avoids the pad-limited designs of earlier packages, where connections were confined to the edges of the die.

  • Multi-component packages integrate several chips into one unit. This saves PCB space and improves performance by keeping interconnects short, compared to placing chips in separate packages.

  • Surface-mount packaging connects the chip to the printed circuit board (PCB) with tiny metal bumps that are melted into place. It supports many more connections and allows components on both sides of the board, replacing older methods where long pins went through drilled holes.

  • Fan-out packaging routes signals outward beyond the die footprint, enlarging the package but enabling many more connections. It evolved from fan-in designs, where signals were routed inward to keep the package size close to the die (chip-scale packaging).

  • Redistribution layers (RDLs) are extra wiring layers inside the package that take the chip’s tightly packed connection points and spread them out so they can attach to the printed circuit board (PCB).

New Advances in Packaging

The field of advanced packaging is progressing on many fronts at once, from how different chips are combined and bonded to new materials, cooling strategies, and reliability improvements. The categories below highlight the main areas where engineers are pushing the boundaries.

Heterogeneous integration makes it possible to combine different types of chips in a single package. After decades of development, 3D packaging technologies are becoming one of the key enablers of heterogeneous integration and are now reaching maturity and moving into practical use. This progress also brings challenges, such as uneven aging, warpage, and mechanical stress.

Leadframes are thin metal sheets that provide both mechanical support and electrical pathways. Once mainly used for low-cost packaging, they are now being adapted for high-performance applications, with new designs that allow denser connections and the integration of multiple chips.

Bonding (the process of attaching and electrically connecting chips inside a package) can be achieved through different methods, and these are diversifying. Wirebonding remains widely used, but other approaches are advancing. Thermocompression bonding and laser-assisted bonding enable more precise chiplet integration. Hybrid bonding is emerging as one of the most promising techniques for 3D stacking.

Interposers and bridges are increasingly used to improve connectivity between chips. Acting as intermediate connection layers, they enable shorter and denser wiring that improves performance and lowers power. Work is ongoing with silicon, organic, and glass interposers, each offering different tradeoffs in cost, precision, and signal isolation.

Panels represent a new approach where large rectangular substrates are used instead of circular wafers. This makes it possible to process more chips at once and lower costs. The main advancement here is fan-out panel-level packaging (FOPLP), which extends this method and aims to reduce assembly costs further if yields can be scaled.

Assembly methods include the processes used to put package components together. The key development is the introduction of Package Assembly Design Kits (PADKs), which bring more standardization to the design process. By checking connectivity and reliability upfront, PADKs help reduce errors, improve yields, and shorten cycle times.

Thermal management is becoming more critical as power density continues to rise and chips generate more heat in smaller areas. One approach under development is package-integrated vapor chamber heat spreaders, which are built directly into the package and provide much lower thermal resistance than conventional cooling methods.

Reliability challenges are also in focus. Thinner dies improve performance but make chips more fragile, increasing risks such as warpage, where the die bends or twists out of shape, die-pop, where the die separates from the package during assembly, and electromigration, the gradual wearing down of metal interconnects under high current. Optimized reflow processes are helping to reduce these defects and improve long-term reliability.

Source: Advanced Packaging Fundamentals (SemiEngineering, 2025)

Spotlights

HSBC and IBM ran the first publicly disclosed hybrid quantum–classical trial on production-scale trading data in the European corporate bond market. Using IBM’s Heron quantum processor integrated with classical workflows, the system achieved up to 34% improvement in predicting quote-fill probabilities compared to standard statistical models. The trial targeted RFQ optimisation in OTC bond trading, where pricing signals are noisy and multi-factorial. Results suggest that near-term quantum processors, when combined with classical methods, can enhance market-making strategies by uncovering patterns classical approaches alone miss.

imec announced two major breakthroughs in single-patterning High-NA EUV, a next-generation chip manufacturing technology. It created 20nm-pitch metal line structures with 13nm spacing, needed for future interconnect layers, and demonstrated ruthenium lines at 20nm and 18nm pitch using a new etching process. The latter achieved a 100% electrical yield, proving the structures can function reliably. These advances mark an important step toward sub-2nm logic nodes, helping reduce manufacturing steps and costs compared to today’s multi-patterning techniques, and strengthening Europe’s roadmap for advanced semiconductor scaling.

Headlines


Last week’s headlines featured semiconductor developments from infrastructure deals to space-grown materials and new transistor designs, a landmark proof of quantum advantage with advances in qubits and quantum internet, and further updates in photonic, neuromorphic, data centers, cloud, and AI.

⚛️ Quantum

⚡️ Photonic / Optical

🧠 Neuromorphic

💥 Data Centers

☁️ Cloud

🤖 AI

Readings


This week’s reading list looks at AI’s evolving role in chip design, chiplet interoperability, global quantum computing trends, new momentum in photonics, advances in spiking neural networks, and novel cooling approaches for AI data centers.

🦾 Semiconductors

The Limits of AI’s Role in EDA Tools (SemiEngineering) (16 mins)

Benefits and Challenges of Using Chiplets (SemiEngineering) (14 mins – Video)

⚛️ Quantum

⚡️ Photonic / Optical

🧠 Neuromorphic

💥 Data Centers

Funding News


Last week’s financings ranged from early Seed and Series A rounds in encryption, cooling, and quantum to several large later-stage raises. The standout was Nscale’s $1.1B Series B in data centers, alongside significant activity in semiconductors and connectivity.

Amount

Name

Round

Category

£4.6M

Delta.g

Seed

Quantum

$6M

Belfort

Seed

Encryption

$14M

NanoQT

Series A

Quantum

$24M

Corinits

Series A

Cooling

$59M

Morse Micro

Series C

Connectivity

$250M

Modular 

Series C

Semiconductors

$140M+

Empower Semiconductor

Series D

Semiconductors

$1.1B

Nscale

Series B

Data Centers

Bonus: Nvidia’s $100B Bet on OpenAI and the Data Center Race

Nvidia’s plan to invest up to $100B in OpenAI is one of the largest private bets yet on AI infrastructure. The deal centers on deploying 10 gigawatts of Nvidia systems for OpenAI’s next generation of data centers and signals a shift in OpenAI’s reliance away from Microsoft toward a broader set of partners.

Alongside this, OpenAI is advancing its Stargate project with Oracle and SoftBank, with estimates placing its total buildout costs at as much as $850B.

Alibaba is also expanding its global cloud footprint, while policy experts are examining how AI infrastructure could both strain and strengthen the electric grid. Oracle, meanwhile, is taking on significant debt to finance its role in the AI data center build-out.

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