🦾 Advanced Packaging Pt. 3 - The Thermal Management Bottleneck

A Newsletter for Entrepreneurs, Investors, and Computing Geeks

Author

Emily Eisenblätter
October 20, 2025

Happy Monday! Here’s what’s inside this week’s newsletter:

  • Deep dive: The third part of our advanced packaging series examines how rising chiplet power and 3D stacking create thermal bottlenecks, and the new materials and cooling technologies needed to address them.

  • Spotlights: Apple’s new M5 chip, delivering a major leap in AI performance and efficiency, and Nvidia’s growing role as a leading investor in the AI ecosystem.

  • Headlines: Major semiconductor updates from Intel, Arm, and AMD, breakthroughs in quantum and photonics from China and Europe, advances in neuromorphic, and record data center and infrastructure deals.

  • Readings: Shifts in the memory market, advances in semiconductor metrology, broadband quantum memory, edge photonic circuits, neuromorphic hardware trends, and new approaches to cooling and power efficiency in AI data centers.

  • Funding news: A quieter week overall, with fewer large rounds than usual. Activity centered on early-stage quantum and photonics startups, while semiconductors led in scale with Tachyum’s $220M Series C.

  • Bonus: Key highlights from the Open Compute Project (OCP) Summit in San Jose, where open standards and modular architectures are setting the direction for next-generation AI infrastructure.

Check out our website for the Future of Computing Conference in Paris on November 6 to see the full agenda and pitching startups. If you’d like to join us, you can sign up here âť¤ď¸Ź

Deep Dive: Advanced Packaging Pt. 3 - The Thermal Management Bottleneck

This deep dive is the third part of our exploration of advanced packaging. In the first edition, we covered the fundamentals: why packaging matters, what drives its adoption, and the most recent innovations in the field.

The second part examined how advanced packages are organized through 2D, 2.5D, and 3D integration, along with the role of interposers in enabling these dense chip-to-chip links.

With part of the architectural complexity now established, this part turns to thermal management: the physical constraint that increasingly defines what advanced packaging can realistically support. As chiplets stack and power densities rise, managing heat has become a primary limiter, not a secondary engineering task.

Thermal Challenges

  • Rising Chiplet Power Density: Increased transistor concentration within individual chiplets creates localized heat, shifting the challenge from overall package power to concentrated thermal hotspots.

  • Stacking and Reduced Heat Paths: Vertical die stacking limits surface area for heat extraction and increases thermal resistance to the cold plate, resulting in higher thermal density within the stack.

  • Heterogeneous Layout Tradeoffs: Integrated compute, memory, and power IP produce different thermal profiles, requiring tradeoffs, as improving thermals in one region can worsen conditions in another under variable workloads.

  • High-Speed IO in Base Dies: Higher power densities in IO blocks (input/output interfaces), when placed in base die layers, face increased dissipation difficulty due to interconnect and dielectric barriers.

  • Thinner Silicon and Interface Sensitivity: Silicon thinning (from roughly 700 µm to 50 µm) reduces lateral heat spreading and increases sensitivity to thermal defects.

Thermal Requirements

  • Thermal Interface Materials (“TIMs”): Current efforts focus on lowering thermal resistance at critical interfaces within the package. Looking ahead, requirements include up to a 50% reduction and a transition toward embedded cooling without traditional interface materials.

  • Heat Spreaders: Materials with higher thermal conductivity than copper are needed, while maintaining manufacturability. Over time, these spreaders must integrate directly into stacked architectures rather than sitting above them.

  • Cooling Solutions: System-level cooling is shifting from air-based CRAC (Computer Room Air Conditioning) units toward direct liquid cold plates at the package. Future approaches include above-ambient and sub-ambient cooling, ultimately requiring heat removal from within stacked dies.

  • Metrology: Future thermal solutions require non-destructive measurement with approximately 3 °C accuracy to characterize thermal behavior across bonded layers, including x-y-z conductivity (across horizontal and vertical heat paths).

  • Modeling: Multiphysics thermal modeling is needed to simulate conductivity and heat flow in stacked architectures, capturing material interactions and enabling design validation before fabrication.

Thermal management has shifted from a packaging afterthought to a determining factor in system architecture. As transistor counts and stack depths increase, managing localized heat becomes as critical as delivering power or routing signals. Future compute systems will depend on co-design of cooling, materials, and workload profiles, making thermals a central pillar of advanced packaging.

Spotlights

“Apple today announced M5, delivering the next big leap in AI performance and advances to nearly every aspect of the chip. Built using third-generation 3-nanometer technology, M5 introduces a next-generation 10-core GPU architecture with a Neural Accelerator in each core, enabling GPU-based AI workloads to run dramatically faster, with over 4x the peak GPU compute performance compared to M4. The GPU also offers enhanced graphics capabilities and third-generation ray tracing that combined deliver a graphics performance that is up to 45 percent higher than M4. M5 features the world’s fastest performance core, with up to a 10-core CPU made up of six efficiency cores and up to four performance cores.”

The article outlines how Nvidia has rapidly expanded its role as an AI investor, using its record profits to take stakes in leading startups. It explains Nvidia’s stated goal of backing “game changers and market makers” and lists the major million- to billion-dollar rounds it has joined since 2023 including xAI, Mistral AI, Reflection AI, Thinking Machines Lab, and Figure AI.

Headlines


Last week’s headlines featured major semiconductor and AI hardware moves, breakthroughs in quantum and photonic computing, advances in neuromorphic systems, and record deals reshaping global data center infrastructure.

⚛️ Quantum

⚡️ Photonic / Optical

🧠 Neuromorphic

đź’Ą Data Centers

And again: Read more about Starcloud in our recent interview!

📡 Networking

Readings


This week’s reading list covers shifts in the memory market, advances in semiconductor metrology, broadband quantum memory, edge photonic circuits, neuromorphic market trends, and new approaches to power and cooling in AI data centers.

🦾 Semiconductors

⚛️ Quantum

⚡️ Photonic / Optical

🧠 Neuromorphic

đź’Ą Data Centers

Improving AI Efficiency in Data Centres (Power Dynamic Response) (23 mins)

Funding News


Last week’s financings were concentrated in quantum and semiconductors with fewer large-scale rounds than usual. Quantum saw a series of early-stage rounds, while semiconductors dominated in scale with Tachyum’s $220M Series C.

Amount

Name

Round

Category

€2M

SiC Systems

Pre-Seed

Qantum

€7.5M

Isentroniq

Venture Round

Quantum

€8M

LuxQuanta

Series A

Quantum

$11M

Vertical Semiconductor

Seed

Semiconductors

$30M

Prisma Photonics

“Growth Round” 

Photonics

$40M

Movandi

Venture Round

Networking

$220M

Tachyum

Series C

Semiconductors

Bonus: Highlights from the Open Compute Project (OCP) Summit

This week’s OCP Summit in San Jose showcased how open hardware standards are now guiding the future of AI infrastructure. Instead of proprietary systems, the industry is aligning around shared blueprints for rack power, chiplet integration, and Ethernet-based interconnects. Below are the key developments that signal where hyperscale infrastructure is heading:

Open Standards & Infrastructure Blueprints

Chiplet & Modular Silicon Ecosystem

Power, Racks & Efficiency Platforms

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